ïÔ: D&R SoC News Alert [SoC-NewsAlert@design-reuse.com]
ïÔÐÒÁ×ÌÅÎÏ: 11 ÉÀÌÑ 2005 Ç. 21:48
ëÏÍÕ: Michael Dolinsky
ôÅÍÁ: D&R SoC News Alert - July 11, 2005
DR SoC News Alert
Design And ReuseDesign And ReuseDesign And Reuse
EETimes Network
July 11, 2005    


WELCOME
Michael,
Welcome to the issue of July 11, 2005 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

SPONSORED BY: TRUE CIRCUITS, INC.

True Circuits, Inc. offers a family of award-winning clock generator, deskew, low-bandwidth and spread-spectrum PLLs and DDR DLLs that spans nearly all performance points and features typically requested by ASIC and FPGA designers.
These high-quality, low-jitter, silicon-proven hard macros are available for immediate delivery in a range of frequencies, multiplication factors, sizes and functions in TSMC, UMC and Chartered processes from 0.25um to 90nm.
Call (650) 691-2500 or visit http://www.truecircuits.com/dr9.

NEW IP/SOC PRODUCTS
Multi-format Encoder (MPEG-4, H.263, H.264/AVC & JPEG) from Hantro Products Oy
20-bit, 93dB Dynamic Range, 8 to 48 kHz Sampling Frequency Stereo Audio Codec w/ Multiple Analog IOs and Digital Sound Effects from ChipIdea Microelectronics
10 Gigabit BASE-R Physical Coding Sublayer from Mentor Graphics
Low Power Elliptic Curve Point Multiplier Core from Elliptic Semiconductor
Programmable inner-receiver processor optimised for OFDM systems from Silicon Hive
PCI Express Endpoint Controller Core from CAST
1.5V Fixed Output Low Drop-Out Regulator from Onyx Semiconductor Solutions Corp.
USB 2.0 On-the-Go software stack from VinChip Systems
INDUSTRY ARTICLES
Simultaneous Exploration of Power, Physical Design and Architectural Performance Dimensions of the SoC Design Space using SEAS
Using a "DSP-free" design for VOIP-enabled end-points
Improving yield in RTL-to-GDSII flows
Efficient Verification of CAN based System
AICP: AURA Intelligent Co-processor for Binary Neural Networks
COMMENTARY/ANALYSIS
The RISC that did not pay off
Making the switch from NOR to NAND flash
Structured ASICs deserve serious attention at 90 nm
Customers using ASICs move to 32-bit MCUs
IN THE NEWS
IP/SOC PRODUCTS
RF Engines releases a library of high performance FFT Cores for FPGA
TELEVISION IP: Programmable core boosts processing On Demand
Rambus Unveils Next Generation XDR Memory Interface
CHIPIDEA announces a new HDTV AFE product line
DESIGN PLATFORMS / STRUCTURED ASIC
Synplicity Continues Platform ASIC Design Innovation With Enhanced Amplify RapidChip Software
Synplicity Delivers Pro Version of its Amplify ISSP Software to NEC Electronics' Customers
DEALS
Chipnuts Technology Leverages the Power of Zsp500 Licensable Dsp Core for Wireless Applications
QLogic incorporates Rambus PCI Express Digital Controller in 4G Fibre Channel ASICs
ARC International Signs Licensing Agreement with a Leading Smartcard Technology Provider
Wavesat Selects SafeNet for Next-Generation WiMAX OEM platform
FINANCIAL RESULTS
Transmeta Expects to Report Positive Operating Cash Flow for the 2005 Second Quarter
Faraday Monthly Sales Report - June 2005
TSMC Monthly Sales Report -- June 2005
NEC Electronics Announces Forecast of First Quarter Financial Results and Revisions to Interim and Full-Year Forecasts
ARC International plc Announces Trading Update for the Six Months Ended June 30, 2005
DESIGN SERVICES
eInfochips to tap into DSP growth strengthens Texas Instruments collaboration
EMBEDDED SYSTEMS
Akita Electronics, Chipcon AS and Figure 8 Wireless Announce OEM Development Modules Based on Chipcon's CC2420 RF Platform
CSR brings Bluetooth to stereo headphones for the iPod; DSP-based designs with native MP3 support result in twice the battery life
Accelerated Technology’s Nucleus IPsec Encrypts and Safeguards Sensitive Data Sent Over the Internet
Embedded Control Market Lights up the Sky
TTPCom demonstrates its multiplatform credentials with Intel on the O2 XM handset
FOUNDRIES
Shift to 65 nm has its costs
TSMC and Kodak Sign License Agreement for CMOS Image Sensors
FPGA/CPLD
Xilinx AcceleratesVirtex-4 FPGA Performance By An Additional 26% With New Xplorer Utility
Actel's Libero IDE Delivers Unmatched Value, Flexibility and Efficiency for Complex FPGA-Based Designs
Cypress Delivers Programmable System-on-Chip(TM) (PSoC(TM)) with Integrated Full-Speed USB
Actel Introduces Land Grid Array Packaging Option for Radiation-Tolerant RTAX-S FPGA Family
Xilinx prepares to boost FPGA activity in India
OTHER
LogicVision Showcases High-Speed I/O Test Technology at SEMICON West Conference

NEW ON D&R WEB SITE

DSP on FPGA Corner :
This DSP Hot Corner explores if technology-optimized DSP IP or technology-independent IP generated/optimized by DSP Synthesis can meet the design requirements when mapped onto an FPGA.
In Cooperation with Synplicity


D&R Silicon IP / SoC Catalog :
The world's largest directory of Silicon IP (Intellectual Property), SoC Configurable Design Platforms and SOPC Products from 200 vendors

D&R IP Packaging, IP Reuse and Delivery Station :
D&R provides to the market the best intranet IP packaging and IP transfer solution compatible with any DDM and IP repository you have in house



Search for Silicon IP

Search for Verification IP

Search for Software IP

Find an Expert

Industry Articles

Latest News

Tool Demos

Free IP Cores


DESIGN AND REUSE S.A.

Corporate Headquarters:
12 rue Ampere
BP 267
38 016 Grenoble Cedex 1
FRANCE
Tel: +33 476 21 31 02
Fax: +33 476 49 00 52

US office:
5600 Mowry School Road
Suite 180
Newark, CA 94560
USA
Tel: +1 510 656 1445
Fax: +1 510 656 0995


REGISTER:
If this newsletter was forwarded to you by a colleague, you can have it sent directly to you at no cost. To register for D&R SoC News Alert, go to: http://www.us.design-reuse.com/users/signup.php

UPDATE YOUR PROFILE / UNSUBSCRIBE :
You are subscribed as dolinsky@gsu.by and you receive this Alert once a week in html format.

* If you wish to unsubscribe, you can do it there: http://www.us.design-reuse.com/users/alert.php?u=32546&e=dolinsky@gsu.by

* If you need to change the e-mail address at which you receive this newsletter, you can do it there

* If you need to update your user profile for receiving this letter on another time basis or in another format, you can do it there:
http://www.us.design-reuse.com/users/alert.php?u=32546&e=dolinsky@gsu.by

The SoC News Alert can be delivered :
- Twice a week, once a week or once a month
- In html or text format

COMMENTS / SUGGESTIONS / QUESTIONS:
Anything about the contents of this alert can be directed to : support@design-reuse.com

PASS IT ON. . .
Feel free to forward this newsletter to your colleagues.